Verification is an important step in the process of designing and creating an electronic product. Verification ensures that the electronic design will work for its intended purpose, and is usually performed at several stages of the electronic design process. Circuit designers and verification engineers use different methods and analysis tools to verify circuit designs, including simulation. Simulation dynamically verifies a design by monitoring computed behaviors of the design with respect to test stimuli.
As analog content increases in integrated circuit design, the complexity of mixed signal design and verification also increases. As a result, electronic design automation (EDA) tool vendors are introducing additional design and verification approaches into broader design flows. Assertion Based Verification (ABV) helps designers and verification engineers improve design quality and reduce time to market. ABV techniques are becoming more widespread in design and verification, particularly those using Property Specification Language (PSL) and SystemVerilog Assertions (SVA).
PSL is a language developed for specifying formally verifiable properties or assertions about hardware designs. SVA is the SystemVerilog assertion specification language, which is similar to PSL. SystemVerilog is a combined hardware description language and hardware verification language based on extensions to Verilog, which in turn is a standardized hardware description language used to model electronic systems. VHDL is another hardware description language known in the art. For ease of reference, this application will simply refer to “Verilog” throughout to encompass hardware description languages and hardware verification languages in general, in contrast to SPICE type circuit simulations.
Assertions may be annotations in a design that perform built-in “checks” of logical properties during verification, and are often implemented as statements that describe expected design behavior. An assertion may thus be a predicate (i.e., a true-false statement) placed at a point to indicate that the designer thinks that the predicate is always true at that point. Assertions allow designers to express complex relationships among design components.
For example, an assertion may be used to verify that an assumption made during a design implementation remains valid when the design is verified. If an assertion evaluates to false during verification, an assertion failure results. Such a failure may draw attention to the location of the logical inconsistency. A major advantage of this technique is that when an error does occur it may be detected immediately and directly, rather than through its often obscure side effects. Since an assertion failure usually reports the design code location, debugging is simplified. Assertions may be entered by the circuit designer or added by a separate process.
Assertions may be verified statically or dynamically. Dynamic verification involves applying a stimulus to a circuit design, often a time-varying stimulus processed by a simulator. Simulators thus may be considered to be effectively synonymous with dynamic verification tools. When a verification tool processes the design, the assertions may be extracted as part of a test bench and used in checking the circuit for assertion violations. Assertions may be written both during development of the design and in the verification environment. Both designers and verification engineers may be involved in identifying design requirements and capturing them as assertions.
Assertions have historically been used for digital circuit designs, but EDA vendors are beginning to add such digital technologies to dynamic analog verification tools. Different simulator types have inherent differences that make it difficult to automatically determine whether an assertion implemented in one simulator is functionally equivalent to another simulator's implementation. For example, the SPICE type simulators widely used in analog circuit simulation were not originally designed for assertion based verification techniques with PSL/SVA assertions. ABV implementation in such analog simulators is by necessity sufficiently different from the digital implementation to make direct comparisons difficult or impossible.
Further, SPICE and Verilog simulators/verification tools represent analog and digital circuit objects, respectively, in their own domains. Verilog handles digital signals versus the circuit branch currents and node voltages used by SPICE. Verilog uses event driven simulation algorithms versus the SPICE continuous time algorithms, resulting in possible timing differences. Differences may also occur due to mistranslation of assertions by a user, e.g., in translating from Verilog to SPICE, or vice versa.
Differences may also be due to faulty implementation of assertion language specifications in one or both simulators by a vendor. Use of one simulator, e.g., a SPICE tool, as a “golden” standard against another simulator, e.g., a Verilog verification tool, may provide insight into any significant simulation implementation differences. Comparison of user-written assertions in otherwise equivalent test benches may also be valuable.
Ensuring the coherence and correlation of ABV implementations and reported assertion results across various widely used simulation platforms has proven challenging. These requirements are necessary both internally to software makers for quality assurance purposes, and externally by users for assertion authoring purposes. Therefore the circuit design industry requires a tool to automatically compare simulated circuit results as determined by different simulators, which may be analog or digital. Accordingly, the inventor has developed such a tool, to verify simulation consistency and detect errors in simulator implementations.